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Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
2008
2008 Symposium on Application Specific Processors
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. Most of these approaches however are confined by basic block level parallelism described within the CDFGs (Control-Data Flow Graphs). In this work we propose a new high-level synthesis flow which can leverage instruction-level parallelism (ILP) beyond the boundary of the basic blocks. We extract statistical
doi:10.1109/sasp.2008.4570781
dblp:conf/sasp/PapakonstantinouCH08
fatcat:iplz35xzbffvfaaoxqpbfx3sau