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We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently proposed instruction packing to SMT. Instruction packing opportunistically packs two instructions (possibly from different threads), each with at most one non-ready source operand at the time of dispatch, into the same issue queue entry. Our second design, termed 2OP_BLOCK, takes these ideas one step further and completelydoi:10.1109/hpca.2006.1598137 dblp:conf/hpca/SharkeyP06 fatcat:pehckrui2bbabef7c3ms6diygi