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Electrical metrics for lithographic line-end tapering
2008
Photomask and Next-Generation Lithography Mask Technology XV
Despite advanced resolution enhancement techniques (RET) and illumination techniques, several sources of variation in the pattern transfer process manifest as variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities. However, lithography simulation is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this work, we
doi:10.1117/12.793117
fatcat:6jptp2mw4vh27ctdr3md24mfby