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Low-power scan design using first-level supply gating
2005
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement
doi:10.1109/tvlsi.2004.842885
fatcat:hwq2k4rh2ff75ggmpo736up3ji