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Proceedings. 42nd Design Automation Conference, 2005.
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths selected with a criterion. While the proposed method generates each two-pattern test for more than one fault in the target fault list as well as ordinary test compaction methods, secondary target faults are selected from the fault list such that many other faults, which may not be included in the fault list, are detected bydoi:10.1109/dac.2005.193933 fatcat:5djv262urvcvfjw5srlz7ppcxu