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Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis
2017
2017 Euromicro Conference on Digital System Design (DSD)
Wormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical real-time applications has not been demonstrated yet. In this paper, in the context of probabilistic timing analysis (PTA), we propose a PTA-compatible wNoC design that provides tight time-composable contention bounds. The proposed wNoC design builds on PTA ability to reason
doi:10.1109/dsd.2017.71
dblp:conf/dsd/SlijepcevicHAC17
fatcat:d3qk7e26jje5lhddxrle3zrede