The circuit and physical design of the POWER4 microprocessor

J. D. Warnock, J. M. Keaty, J. Petrovick, J. G. Clabes, C. J. Kircher, B. L. Krauter, P. J. Restle, B. A. Zoric, C. J. Anderson
2002 IBM Journal of Research and Development  
The IBM POWER4 processor is a 174-milliontransistor chip that runs at a clock frequency of greater than 1.3 GHz. It contains two microprocessor cores, high-speed buses, and an on-chip memory subsystem. The complexity and size of POWER4, together with its high operating frequency, presented a number of significant challenges for its multisite design team. This paper describes the circuit and physical design of POWER4 and gives results that were achieved. Emphasis is placed on aspects of the
more » ... n methodology, clock distribution, circuits, power, integration, and timing that enabled the design team to meet the project goals and to complete the design on schedule. 28 35K The smallest members of the hierarchy are "macros" 100K standard-cell level, the units and then in turn the core and chip are concurrently being floorplanned and timed. Provided that the proper contracts have been created, all of this work can proceed independently and in parallel. Further parallelism of design was employed by separating the design tasks of logic entry and simulation from those of circuit design, floorplanning, and timing. For each of the four hierarchies, the logic design and simulation were able to progress in parallel with the circuit design of that entity, with a final formal verification step to ensure equivalence [5] . Design phases The design process was divided into several successive phases-high-level design, schematic design, and physical design-with increasing refinement of the design occurring at each phase. The design process flows for these phases are shown in Figures 3-5 . At the start of high-level design, the chip was partitioned into chip, core, unit, and macro "blocks" as described above. The high-level logic is written in VHDL and compiled into physical blocks that match this hierarchy. Transistor-level and standard-cell-level design can then be performed in parallel with macro-level simulation and logic entry. Similarly, at the unit, core, and chip levels, floorplanning and even timing can begin in parallel with the higher-level logic design and simulation. The main deliveries from any block owner at this time are "contracts." Contracts are the early size and timing budgets IBM Abstract Netlists Spice Noise rule Layout Custom macros Reports
doi:10.1147/rd.461.0027 fatcat:wp4ojp7zyfam5nhtajbfdfh2uy