ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

Ming-Dou Ker, Hsin-Chyh Hsu
IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings.  
A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in the mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit with the substrate-triggered technique for 2.5V/3.3V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25-µm salicided CMOS
more » ... ess. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ~60% by this substrate-triggered design.
doi:10.1109/soc.2003.1241496 fatcat:l6szpb4w65aplfmamvvcv4hi2y