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Multilevel optimization of pipelined caches
1997
IEEE transactions on computers
This paper formulates and shows how to solve the problem of selecting the cache size and depth of cache pipelining that maximizes the performance of a given instruction-set architecture. The solution combines trace-driven architectural simulations and the timing analysis of the physical implementation of the cache. Increasing cache size tends to improve performance but this improvement is limited because cache access time increases with its size. This trade-off results in an optimization
doi:10.1109/12.628394
fatcat:3cfie5jlzze6pglaepb2cw76iq