Pipelining a triggered processing element

Thomas J. Repetti, João P. Cerqueira, Martha A. Kim, Mingoo Seok
2017 Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-50 '17  
Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements o↵er a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall e ciency. This paper considers the microarchitectural issues surrounding pipelining a spatial processing element
more » ... with triggeredinstruction control. We propose two new techniques to mitigate pipeline hazards particular to spatial accelerators and non-program-counter architectures, evaluating them using invivo performance counters from an FPGA prototype coupled with a rigorous VLSI power and timing estimation methodology. We consider the e↵ect of modern, post-Dennard-scaling CMOS technology on the energy-delay tradeo↵s and identify a set of microarchitectures optimal for both high-performance and low-power application settings. Our analysis reveals the e↵ectiveness of our hazard mitigation techniques as well as the range of microarchitectures designers might consider when selecting a processing element for triggered spatial accelerators.
doi:10.1145/3123939.3124551 dblp:conf/micro/RepettiCKS17 fatcat:ihdzth2hffctfebmxc5ejmzbza