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Pipelining a triggered processing element
2017
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture - MICRO-50 '17
Programmable spatial architectures composed of ensembles of autonomous fixed-ISA processing elements o↵er a compelling design point between the flexibility of an FPGA and the compute density of a GPU or shared-memory many-core. The design regularity of spatial architectures demands examination of the processing element microarchitecture early in the design process to optimize overall e ciency. This paper considers the microarchitectural issues surrounding pipelining a spatial processing element
doi:10.1145/3123939.3124551
dblp:conf/micro/RepettiCKS17
fatcat:ihdzth2hffctfebmxc5ejmzbza