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Linear LMS Compensation for Timing Mismatch in Time-Interleaved ADCs
2009
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
The time-interleaved architecture permits the implementation of high-frequency analog-to-digital converters (ADCs) by multiplexing the output of several time-shifted low-frequency ADCs. An issue in the design of a time-interleaved ADC is the compensation of timing mismatch, which is the difference between the ideal and real sampling instants. In this paper, we propose a compensation method that, as opposite to existing approaches, does not assume that the input signal is band limited but
doi:10.1109/tcsi.2009.2015730
fatcat:quyrw3s77bamppwq3mdjfcqhze