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Combinable memory-block transactions
2008
Proceedings of the twentieth annual symposium on Parallelism in algorithms and architectures - SPAA '08
This paper formalizes and studies combinable memory-block transactions (MBTs). The idea is to encode short programs that operate on a single cache/memory block and then to specify such a program with a memory request. The code is then executed at the cache or memory controller, atomically with respect to other accesses to that block by this or other processors. The combinable form allows combining within the memory system or network. In addition to allowing for the standard set of
doi:10.1145/1378533.1378537
dblp:conf/spaa/BlellochGV08
fatcat:3lnfn755mfhi3l66rgpnojvjdu