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Memory controller policies for DRAM power management
Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
The increasing importance of energy e ciency has produced a m ultitude of hardware devices with various power management features. This paper investigates memory controller policies for manipulating DRAM power states in cache-based systems. We d e v elop an analytic model that approximates the idle time of DRAM chips using an exponential distribution, and validate our model against trace-driven simulations. Our results show that, for our benchmarks, the simple policy of immediatelydoi:10.1145/383082.383118 dblp:conf/islped/FanEL01 fatcat:d7vjlq4ojfbgtfne2pmrq2ttpy