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Efficient VLSI layouts for homogeneous product networks
1997
IEEE transactions on computers
In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length. In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we define a new measure that we call "maximal congestion," that can be used to obtain both the bisection
doi:10.1109/12.628392
fatcat:kkscicreqna4hdquiwwcimizfi