The inter-band tunnel transistor (TFET) architecture features a sub-kT/q sub-threshold slope operation and can potentially support high I ON /I OFF ratios over small gate voltages. Based on twodimensional numerical simulations, we investigate TFET in various material systems ranging from silicon to indium arsenide. TFET performance can be enhanced when heterojunctions are employed at the source side to enhance tunneling, nonequilibrium carrier population is maintained in the channel and one

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... nsional tunneling junction are incorporated. Mixed mode circuit simulations using TFETs highlight the impact of feed forward gate-to-drain capacitance in these devices during transient switching operation and reveal important differences with MOSFETs. Narrow gap semiconductors with low density of states are projected as viable candidates to implement TFET architecture in sustaining an aggressive supply voltage scaling roadmap for future digital logic applications.