A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin

Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide
2007 IEICE Electronics Express  
A 90 nm CMOS, 64 Kbit, 1.16 GHz, 16 port SRAM with multi-bank architecture realizing 590 Gbps random access bandwidth, 41 mW power dissipation at 1 GHz and 0.91 mm 2 (13.9 µm 2 /bit) area consumption is reported. Compared to conventional 16 port SRAM data, area and power consumption are reduced by factors 16 and 5, respectively, while maximum clock frequency is about a factor 2 higher.
doi:10.1587/elex.4.21 fatcat:zbnqejsbhveclewklhctrdvo74