The performance of cache-coherent ring-based multiprocessors

Luis André Barroso, Michel Dubois
1993 Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93  
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective use of powerful microprocessors in shared memory multiprocessor configurations. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessors, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new microprocessors. In this paper we
more » ... uate the performance of the unidirectional slotted ring interconnection for small to medium scale shared memory systems, using a hybrid methodology of analytical models and trace-driven simulations. We evaluate both snooping and directory-based coherence protocols for the ring and compare it to high performance split transaction buses.
doi:10.1145/165123.165162 dblp:conf/isca/BarrosoD93 fatcat:rxg54hrm3fcrtilv2ottirsxxm