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Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective use of powerful microprocessors in shared memory multiprocessor configurations. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessors, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new microprocessors. In this paper wedoi:10.1145/165123.165162 dblp:conf/isca/BarrosoD93 fatcat:rxg54hrm3fcrtilv2ottirsxxm