This paper presents a flipped voltage follower low dropout regulation with dual-feedback loops (DF-FVF LDR). Compared to other FVF LDRs, the multiple functions of error amplifier in DF-FVF LDR contribute to better regulation capability. The dominant pole is set by a small Miller capacitor leading to stable frequency response. Adaptive bias is further adopted to expand the bandwidth as well. Simulation was performed with 0.35 µm CMOS process and the results show that the gain for the shunt

more »

... ck loop is boosted greatly. Load and line regulations are reduced to 5.6 µV/mA and 1.4 mV/V. PSRR is maintained −54 dB at 1 kHz and −24 dB at 100 kHz. When the load current varies between 1 mA and 100 mA within edge time of 1 µs, undershoot and overshoot voltage are 110 mA and 89 mA, and the settling time is only 1.5 µs.