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A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages
2015
International journal of circuit theory and applications
In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is
doi:10.1002/cta.2057
fatcat:6njhvoonbrabfjg5ayatmvd6uy