A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Behzad Ebrahimi, Reza Asadpour, Ali Afzali-Kusha, Massoud Pedram
2015 International journal of circuit theory and applications  
In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is
more » ... d with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Figure 2. Schematics of (a) a conventional 6-T SRAM cell with nMOS access and precharged bitlines (AXN) and (b) the proposed SRAM cell with pMOS access and predischarged bitlines (AXP). B. EBRAHIMI ET AL.
doi:10.1002/cta.2057 fatcat:6njhvoonbrabfjg5ayatmvd6uy