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Performance and power optimization through data compression in Network-on-Chip architectures
2008
High-Performance Computer Architecture
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache banks interconnected through a packet-based Network-on-Chip (NoC) communication fabric. Thus, the NoC plays a critical role in optimizing the performance and power consumption of such non-uniform cache-based multicore architectures. While almost all prior NoC studies have focused on the design of router
doi:10.1109/hpca.2008.4658641
dblp:conf/hpca/DasMNPNIYD08
fatcat:su5ocscq6bhajeqrlqjueltxmm