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In this paper, a novel design of an Ultra Low voltage Carry Gate shall be presented. The main objective is to target the robustness of the presented ciruits. We shall also imply as to what extent these circuits can be improved and what their benefits, compared to conventional topologies, are. The design presented, compared to a conventional CMOS carry gate, is area efficient and high speed. The relative delay of a ULV carry gate lies at less than 3% compared to conventional CMOS carry gate. Thefatcat:qpmkffl3qbee3fythepza2ejge