RTL c-based methodology for designing and verifying a multi-threaded processor

Luc Sèmèria, Renu Mehra, Barry Pangrle, Arjuna Ekanayake, Andrew Seawright, Daniel Ng
2002 Proceedings - Design Automation Conference  
A RTL C-based design and verification methodology is presented which enabled the successful high speed validation of a 7 million gate simultaneous multi-threaded (SMT) network processor. The methodology is centered on statically scheduled C-based coding style, C to HDL translation, and a novel RTL-C to RTL-Verilog equivalence checking flow. It leverages improved simulation performance combined with static techniques to reduce the amount of RTL-Verilog and gate-level verification required during development.
doi:10.1145/513950.513951 fatcat:s3h3m2nudjfitphlzfkubh4mvq