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To face the growing complexity of System-on-Chips (SoCs) and their tight time-tomarket constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemCdoi:10.1109/asp-dac47756.2020.9045568 dblp:conf/aspdac/BusnotSVM20 fatcat:z6ucyqgoonclvaopeieifcypbu