A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf
.
Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models
2020
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
To face the growing complexity of System-on-Chips (SoCs) and their tight time-tomarket constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC
doi:10.1109/asp-dac47756.2020.9045568
dblp:conf/aspdac/BusnotSVM20
fatcat:z6ucyqgoonclvaopeieifcypbu