Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models

Gabriel Busnot, Tanguy Sassolas, Nicolas Ventroux, Matthieu Moy
2020 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)  
To face the growing complexity of System-on-Chips (SoCs) and their tight time-tomarket constraints, Virtual Prototyping (VP) tools based on SystemC/TLM must get faster while keeping accuracy. However, the Accellera SystemC reference implementation remains sequential and cannot leverage the multiple cores of modern workstations. In this paper, we present a new implementation of a parallel and standard-compliant SystemC kernel, reaching unprecedented performances. By coupling a parallel SystemC
more » ... rnel and memory access monitoring, we are able to keep SystemC atomic thread evaluation while leveraging the available host cores. Evaluations show a ×19 speed-up compared to the Accellera SystemC kernel using 33 host cores reaching speeds above 2000 Million simulated Instructions Per Second (MIPS).
doi:10.1109/asp-dac47756.2020.9045568 dblp:conf/aspdac/BusnotSVM20 fatcat:z6ucyqgoonclvaopeieifcypbu