Digitali ntegrated circuitsf abricated in nano-technologies have firsts hown to be more vulnerableto transiente rrors effectst han their predecessors. But they also show effects of stressinduced defectsr esulting in earlyl ife-time failures. In general, power dissipation problems and dielectrics tress, due to high field strength, aret he main reasons for shortened life-time expectations. On theo ther hand, system designersr equire highly reliable and long-time dependableh ardware, for examp le

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... n automotive ap plications. On-linee rror detection andcomp ensation usingeither codeso r, in them ore general case, double or trip le modular redundancy (DMR and TMR), hasb een used for decades, but causesh igher power dissipation in nano-logic, additionalstress, and is therefore no cure in termso f life-time extension. Savings on hardware and power are possible, if resources can be re-allocated to produce local TMR upon demand. However, such techniquesm ay cause sudden signal delay s after the detection of errors, which are not easy to handlei n synchronous systems. In this paper we present a pseudo-TMR ap proach, which has little influenceo n timingin the"good case" and performsaregular error correction within 3 extra clock cy cles under error correction without limits on the fault model .