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We introduce an event-based methodology, and its accompanying simulator ("Xnet") for memristive nanodevicebased neuromorphic hardware, which aims to provide an intermediate modeling level, between low-level hardware description languages and high-level neural networks simulators used primarily in neurosciences. This simulator was used to establish several results on Spike-Timing-Dependent Plasticity (STDP) modeling and implementation with Resistive RAM (RRAM), Conductive Bridge RAM (CBRAM) anddoi:10.1109/nanoarch.2013.6623029 dblp:conf/nanoarch/BichlerRGQ13 fatcat:ldaktbfxnjaexjt4zvrlr7fisq