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Available Task-Level Parallelism on the Cell BE
2009
Scientific Programming
There is a clear industrial trend towards chip multiprocessors (CMP) as the most power efficient way of further increasing performance. Heterogeneous CMP architectures take one more step along this power efficiency trend by using multiple types of processors, tailored to the workloads they will execute. Programming these CMP architectures has been identified as one of the main challenges in the near future, and programming heterogeneous systems is even more challenging. High-level programming
doi:10.1155/2009/741282
fatcat:lkqbeei4ovfchbowk7et2kdp2q