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The impact of hot carriers on timing in large circuits
17th Asia and South Pacific Design Automation Conference
This paper focuses on hot carrier (HC) effects in large scale digital circuits and proposes a scalable method for analyzing circuitlevel delay degradations. At the transistor level, a multi-mode energydriven model for nanometer technologies is employed. At the logic cell level, a methodology that captures the aging of a device as a sum of device age gains per signal transition is described, and the age gain is characterized using SPICE simulation. At the circuit level, the cell-leveldoi:10.1109/aspdac.2012.6165025 dblp:conf/aspdac/FangS12 fatcat:elwpil5ag5harhesj4oj7ufzg4