A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is
Through-silicon-via-aware interconnect prediction model for 3D integrated circuirt
Through-silicon-via (TSV) is one of the major design techniques in three-dimensional integrated circuit (3D IC). Based on the parasitic parameter extraction model, the parasitic resistance-capacitance (RC) parameters for different size TSVs are acquired and validated with Q3D simulation data. Using the results of this model, closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented. Comparative results with 3D net without TSV in various cases showdoi:10.7498/aps.61.068001 fatcat:kl6qut3atrbaniv3td7izgs6ma