Through-silicon-via (TSV) is one of the major design techniques in three-dimensional integrated circuit (3D IC). Based on the parasitic parameter extraction model, the parasitic resistance-capacitance (RC) parameters for different size TSVs are acquired and validated with Q3D simulation data. Using the results of this model, closed-form delay and power consumption expressions for buffered interconnect used in 3D IC are presented. Comparative results with 3D net without TSV in various cases show

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... that TSV RC effect has a huge influence on delay and power of 3D IC, which leads maximum delay and power comsumption to extra increase 10% and 21% on average, respectively. It is crucial to correctly establish a TSV-aware 3D interconnect model in 3D IC front-end design.