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Lecture Notes in Computer Science
This paper presents a methodology for the veri cation of speed-independent asynchronous circuits against a Petri net speci cation. The technique is based on symbolic reachability analysis, modeling both the speci cation and the gate-level network behavior by m e a n s of boolean functions. These functions are e ciently handled by u s i n g Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, t h edoi:10.1007/3-540-60029-9_50 fatcat:yfh2tnovrzhcviy3ubcpgbrtoy