This paper presents a methodology for the veri cation of speed-independent asynchronous circuits against a Petri net speci cation. The technique is based on symbolic reachability analysis, modeling both the speci cation and the gate-level network behavior by m e a n s of boolean functions. These functions are e ciently handled by u s i n g Binary Decision Diagrams. Algorithms for verifying the correctness of designs, as well as several circuit properties are proposed. Finally, t h e

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... y o f o u r v eri cation method has been proven by c hecking the correctness of di erent b e n c hmarks. ? Work supported by CYCIT TIC 94-0531-E and Departament d'Ensenyament d e l a Generalitat de Catalunya. Roig, O.; Cortadella, J.; Pastor, E. Verification of asynchronous circuits by BDD-based model checking of