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A new compact and highly regular redundant binary multiplier employing SD number representation has been developed. The n-bit multiplication time required by the multiplier is proportional to log2n. A modified redundant-to-binary converter has also been proposed, which results in a reduction of the delay time and size of the multiplier. The multiplier adopts a hybrid V-L adder tree structure. The modified Booth's algorithm is employed to reduce the number of partial products to half. For an 8 xdoi:10.6084/m9.figshare.13661072.v1 fatcat:dcd56skcarhpnl5k7bogzud4ea