Design of a New Compact and Regular 8 x 8 Multiplier Using Redundant Binary Number Representation

Mi Lu
A new compact and highly regular redundant binary multiplier employing SD number representation has been developed. The n-bit multiplication time required by the multiplier is proportional to log2n. A modified redundant-to-binary converter has also been proposed, which results in a reduction of the delay time and size of the multiplier. The multiplier adopts a hybrid V-L adder tree structure. The modified Booth's algorithm is employed to reduce the number of partial products to half. For an 8 x
more » ... 8 multiplier employing the modified converter, the chip size is 2096 x 3256 µm2. The multiplication time is measured as 48.9ns using a 2pm design rule. We estimated the multiplication time of a 16 x 16 multiplier to be 70ns using a 2µm design rule, and about 35ns using a 1µm design rule and double layer metal wiring. The estimation of the delay time of a 32 x 32 multiplier is about 70ns using a 1µm design rule and double layer metal wiring.
doi:10.6084/m9.figshare.13661072.v1 fatcat:dcd56skcarhpnl5k7bogzud4ea