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Excessive test power dissipation during scan testing of an SOC may cause reliability and yield concerns for the circuit under test (CUT). We propose an enhanced scan segmentation method using logic cluster controllability (LoCCo) technique for scan chain stitching to reduce test power efficiently. After LoCCo based scan stitching, since the trailing edge of scan chains contain very less switching transitions, we optimize the number of segments needed. This enables segmentation hardwaredoi:10.35940/ijitee.h7428.078919 fatcat:ghuuipxvdfcvhjcs4f3phiqjmi