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Memory operations have a significant impact on both performance and energy usage even when an access hits in the level-one data cache (L1 DC). Load instructions in particular affect performance as they frequently result in stalls since the register to be loaded is often referenced before the data is available in the pipeline. L1 DC accesses also impact energy usage as they typically require significantly more energy than a register file access. Despite their impact on performance and energydoi:10.1145/2670529.2754960 dblp:conf/lctrts/BardizbanyanSWL15 fatcat:rp5cnyxtjbhjxeohqjyxs5uwnm