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Implementation of a Hermitian decoder IC in 0.35 /spl mu/m CMOS
2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)
River Rd., Essex Junction, VT 05452 ashbrookQus. ibni. coin A b s t r a c t This paper presents t,he first integrated circuit implementation of a Hermitian dwoder thereby proving its practical viability. Hermitian codes provide much larger block lengths ( n = 4080) compared to that of the popular Reed-Solomon (RS) codes ( n = 256) over the same field (GF (256) ). This translates to a coding gain of 0.6 dB for the same rate. However, Hermitian codes were deemed to be too complex t o implement
doi:10.1109/cicc.2001.929782
fatcat:5vw7vxt745benmhw5tel77hmfm