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A Low-Power Low-Swing Single-Ended Multi-Port SRAM

Hao-I Yang, Ming-Hung Chang, Ssu-Yun Lai, Hsiang-Fei Wang, Wei Hwang
2007 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  

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In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles. Meanwhile, data can be easily written because of floating virtual ground and 1-T equalizer insertion within cell. Low-swing writing ability is achieved by these two approaches. A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability. A
more » ... w-swing 3-port 64x32-bit SRAM macro is simulated in TSMC 130nm CMOS Figure 1 . Traditional 5-T SRAM cell structure. technology. It consumes a minimum of 725MW and 658MW per-port at 1GHz with 1.2V supply voltage for read and write EQ power, respectively. WL 1-4244-0583-1/07/$20.OO ©C2007 IEEE
doi:10.1109/vdat.2007.373203 fatcat:ox2dwltr5vdsnne4vpdm363vsa
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Hao-I Yang, Ming-Hung Chang, Ssu-Yun Lai, Hsiang-Fei Wang, Wei Hwang. "A Low-Power Low-Swing Single-Ended Multi-Port SRAM." 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) (2007)