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A methodology for optimizing buffer sizes of dynamic dataflow fpgas implementations
2014
2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)
Minimizing buffer sizes of dynamic dataflow implementations without introducing deadlocks or reducing the design performance is in general an important and useful design objective. Indeed, buffer sizes that are too small causing a system to deadlock during execution, or dimensioning unnecessarily large sizes leading to a resource inefficient design are both not a desired design option. This paper presents an implementation, validation, and comparison of several buffer size optimization
doi:10.1109/icassp.2014.6854554
dblp:conf/icassp/RahmanBAM14
fatcat:ustipfc2qjai7a7ehyc2hrz73e