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This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGAdoi:10.1145/1084834.1084870 dblp:conf/codes/KruijtzerGRAHJS05 fatcat:e2vqtwo4nvec3ohr7vp4xmepky