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Parallel Programming Model for the Epiphany Many-Core Coprocessor Using Threaded MPI
[article]
2015
arXiv
pre-print
The Adapteva Epiphany many-core architecture comprises a 2D tiled mesh Network-on-Chip (NoC) of low-power RISC cores with minimal uncore functionality. It offers high computational energy efficiency for both integer and floating point calculations as well as parallel scalability. Yet despite the interesting architectural features, a compelling programming model has not been presented to date. This paper demonstrates an efficient parallel programming model for the Epiphany architecture based on
arXiv:1506.05442v1
fatcat:edidr7vxd5cglgeaieprywbdgm