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Register Free Polar Codes Based Partially Parallel Encoder and Decoder Architecture
2016
Indian Journal of Science and Technology
This paper presents about the partially parallel encoder and decoder architecture for polar-codes using register-free technique. In this paper, the folding transformation technique and register minimization technique are used for this architecture to reduce the circuit and timing complexity. In general, the polar codes are referred to a low complexity code to achieve the performance of channel carrying capacity in a binary-input memory-less channels. In the fully-parallel architecture, the
doi:10.17485/ijst/2016/v9i29/93498
fatcat:u2qxjfab3bh6je3dq4kfallbm4