Now a days VLSI application speed and area reduction is very important one. In this paper implemented AES algorithm.AES represents an algorithm for advance encryption standard of different operation required in the steps of encryption and decryption. The proposed architecture is based on optimizing area in terms of reducing and improve throughput for design of AES algorithm in VHDL .this paper presents AES-128 bit algorithm design consist of 128 bit symmetric key and XILINX ISE 14.1 project

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... for synthesis and simulation of this proposed design Keyword: advance encryption algorithm (AES); VHDL; FPGA; encryption and decryption