A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2016; you can also visit the original URL.
The file type is application/pdf
.
Evaluation of the raw microprocessor: an exposed-wire-delay architecture for ILP and streams
Proceedings. 31st Annual International Symposium on Computer Architecture, 2004.
This paper evaluates the Raw microprocessor. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance in the face of increasing wire delays. Raw approaches this challenge by implementing plenty of on-chip resources -including logic, wires, and pins -in a tiled arrangement, and
doi:10.1109/isca.2004.1310759
dblp:conf/isca/TaylorLMWBGHJKPSSSFAA04
fatcat:evq77vdnyza53nak4egrzvlvlq