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Generation Of Software Tools From Processor Descriptions For Hardware/software Codesign
Proceedings of the 34th Design Automation Conference
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development tools would work for commercial DSP processors and microprocessors. The processor instruction set was described using a language called nML. The TMS320C50 DSP processor and the ARM7 microprocessor were modeled in nML. The resulting instruction set models execute about 25,000 instructions per second, and compiled
doi:10.1109/dac.1997.597162
fatcat:hmk6au5a6fa2phvqhg7eja2txq