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Clock period minimization of semi-synchronous circuits by gate-level delay insertion
1999
Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)
A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio of the cycles on the circuit gives a lower bound of the clock period. We show
doi:10.1109/aspdac.1999.759775
dblp:conf/aspdac/YodaTK99
fatcat:p7gbievxnrfhlcpippqz4xn4sa