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In this thesis, we propose a new reconfigurable computer substrate: diastolic arrays. Diastolic arrays are arrays of processing elements that communicate exclusively through First-In First-Out (FIFO) queues, and provide hardware support to guarantee bandwidth and buffer space for all data transfers. FIFO control implies that a module idles if its input FIFOs are empty, and stalls if its output FIFOs are full. The timing of data transfers between processing elements in diastolic arrays isdoi:10.1109/iccad.2008.4681615 dblp:conf/iccad/ChoCKSD08 fatcat:bmtsgrtdora7vh5hgexbpii2wa