A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition

Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Kai-Ting Chang
2014 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65
more » ... nm CMOS technology, the chip size is 0.92 . The PLL locking time is less than 3 . This chip drains 24 mW from a 1.2 V power supply.
doi:10.1109/tcsi.2013.2295016 fatcat:epknyqbiojft7mzt5na7sfeyii