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Power optimizations for the MLCA using dynamic voltage scaling
2005
Proceedings of the 2005 workshop on Software and compilers for embedded systems - SCOPES '05
Power Optimizations for the MLCA Using Dynamic Voltage Scaling The Multi-Level Computing Architecture (MLCA) is a novel architecture for parallel systems-on-a-chip. We propose and evaluate a profile-driven compiler technique for power optimizations of MLCA applications using dynamic voltage scaling (DVS). Our technique combines dependence analysis of loops with profiling in order to identify the slack in parallel execution of coarse-grain tasks. DVS is applied to slow down processors executing
doi:10.1145/1140389.1140401
dblp:conf/scopes/MatosevicAKM05
fatcat:h5hpabudg5dmxkzdhiv2i6kpx4