Asynchronous Design for Parallel Processing Architectures [report]

Teresa H. Meng
1991 unpublished
JAN 0 q. Phone Number: (415) 725-3636 -' E-Mail Address: Goal: The objective of this research is to provide an interconnect synthesis methodology 0 which facilitates a modular design approach without compromising the global performance. The main tasks of this effort will be the development of the theory for optimal C interconnect circuit synthesis from a high-level specification, with emphasis on testability and fault-tolerance asynchronous interface among concurrently
more » ... omputing hardware, and the application of this design methodology to physical implementations of parallel processing systems. Progress: In the past six months, our major research effort has been directed toward the testability of asynchronous circuits. Testability has become a major design consideration in IC industry and the question that whether asynchronous circuits would simplify the testing I tasks is to be answered. Asynchronous combinational circuits had been shown to be fully : testable with single-stuck-at-faults (SSAFs) if precharged circuits were used for implementation; however, the testability of asynchronous control circuits (sequential circuits with environmental constraints) had not been addressed. Level-sensitive scan-path design can be used to aid testing in asynchronous sequential circuits, but scan-path design usually requires too long a testing delay. We are most interested in incorporating testability directly into circuit synthesis. We co6-ris-e-d tne -rtbrefi estability for two areas of asynchronous design: speedindependent circuits and self-timed circuits. Speed-independent circuits are designed to work independently of the gate delays in the circuits. Self-timed circuits are designed to work assuming that each gate follows a minimum and maximum delay assumption. Both kinds of circuits under the different delay assumptions can be designed to be hazard-free through a synthesis procedure. -We used the property of semi-modularity to show that stuck-at-faults (SAF) are fully testable in a hazard-free speed-independent circuit. Semi-modularity defines that if a transition in a circuit is enabled, then the transition must be fired before it is disabled. We proved that this property is a necessary property of a speed-independent hazard-free circuit by construction. We also proved that the same semi-modularity property is a sufficient condition for a circuit to be self-diagnostic; that is, the circuit will halt itself in response to any SAFs [1]. This important theoretical result states that for speedindependent circuits, designing for testability is no more difficult than designing for hazard-freedom. We have developed a CAD program which accepts a circuits implementation and determines if the circuit is semi-modular, and hence if the circuit is selfdiagnostic to SAFs. '
doi:10.21236/ada230374 fatcat:kbilnsl7hjemnppttaso32rl4a