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The continuing scaling of transistors has increased the number of cores available in current processors, and the number of cores is expected to continue to increase. In such manycore processors, the communication between cores with the on-chip interconnect is becoming a challenge as it not only must provide low latency and high bandwidth but also needs to be cost-effective in terms of power consumption. The communication challenge is not only within a single chip but providing high bandwidth todoi:10.1109/jetcas.2012.2201031 fatcat:3arzyh25zrcybaqc3sqlocus2q