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Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems - CASES '01
Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. This paper presents a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance embedded processors. In contrast to earlier schemes that store compressed variable-length instructions in maindoi:10.1145/502239.502244 fatcat:2zst5i5q5zcebiuivbounr632m