Automatic formal verification for scheduled VLIW code

Xiushan Feng, Alan J. Hu
2002 Proceedings of the joint conference on Languages, compilers and tools for embedded systems software and compilers for embedded systems - LCTES/SCOPES '02  
VLIW processors are attractive for many embedded applications, but VLIW code scheduling, whether by hand or by compiler, is extremely challenging. In this paper, I extend previous work on automated verification of low-level software to handle the complexity of modern, aggressive VLIW designs, e.g., the exposed parallelism, pipelining, and resource constraints. I implement these ideas into two prototype tools for verifying short sequences of assembly code for TI's C62x family of VLIW DSPs and
more » ... itsu's FR500 VLIW processor, and demonstrate the effectiveness of the tools in quickly verifying, or finding bugs in, several difficult-to-analyze code segments. ii Contents Abstract ii Contents iii List of Tables vi List of Figures vii It has been a great privilege to be supervised by Alan J. Hu, who was and is an inspiration to me in many ways. Without his ideas and encouragement, my research would not have been nearly as successful. Some of the material in this thesis was prepared in collaboration with Alan J. Hu as a paper for the ACM SIGPLAN Joint Conference LCTES/SCOPES'02. viii To my parents, for their endless patience and support. ix Chapter 1 Description Program Address Generate Determine address of the fetch packet. Program Address Send Send address of the fetch packet to memory. Program Wait A program memory access is performed. Program Data Receive Fetch packet received by CPU. Dispatch Determine the next execute packet in the fetch packet and send it to the appropriate functional units. Decode Decode instructions in functional units. Execute 1 Evaluate predicates. Read operands. For load and store instructions, do address generation and write address modifications to register file. For branch instructions, affect the Program Address Generate stage. For singlecycle instructions, write results to a register file.
doi:10.1145/513829.513844 dblp:conf/lctrts/FengH02 fatcat:cgw473q6rbbgvlbczahsn2q734