Comparative Performance Analysis of High Speed Low Power Area Efficient FIR Adaptive Filter

Manish Jaiswal
2014 IEIE Transactions on Smart Processing and Computing  
This paper presents the comparative performance of an adaptive FIR filter for a Delayed LMS algorithm. The delayed error signal was used to obtain a Delayed LMS algorithm to allow efficient pipelining for achieving a small critical path and area efficient implementation. This paper presents hardware efficient results (device utilization parameters) and power consumed. The FPGA families (Artix-7, Virtex-7, and Kintex-7) for a low voltage perspective are shown. The synthesis results showed that
more » ... e artix-7 CMOS family achieves the lowest power consumption of 1.118 mW with 83.18 % device utilization. Different Precision strategies, such as the speed optimization and power optimization, were imposed to achieve these results. The algorithm was implemented using MATLAB (2013b) and synthesized on the Leonardo spectrum.
doi:10.5573/ieiespc.2014.3.5.267 fatcat:x4bx65aaendfvnrskcwm2q62uq